1. Field of the Invention
This invention relates to an insulated gate thyristor used as a power switching device.
2. Description of the Related Art
Thyristors have been used as devices indispensable for large-capacity applications because of the low on-state voltage characteristic of the thyristors. Nowadays, gate turn-off (GTO) thyristors are often used as high-voltage and large-current area devices. However, it is becoming obvious that the GTO thyristor has disadvantages in (1) that it requires a large gate current to turn off, namely, provide a small turn-off gain and (2) that it requires a large snubber circuit to safely turn off. Since the GTO thyristor does not show a current saturation characteristic in its current and voltage characteristics, passive parts such as a fuse must be connected for load short-circuiting protection, leading to a large bottleneck in system miniaturization and cost reduction. The MOS controlled thyristor (MCT) of a voltage-driven thyristor published on IEEE IEDM Tech. Dig. 1984. p.282 by V. A. K. Temple has been analyzed in characteristics and improved in various laboratories and institutes in the world since then, because the MCT, which is voltage-driven, needs an exceptionally easy gate circuit and shows a low on-state voltage characteristic as compared with the GTO thyristor. However, like the GTO thyristor, the MCT does not show a current saturation characteristic, thus requires passive parts such as a fuse in practical use.
Doctor Pattanayak et al disclosed in U.S. Pat. No. 4,847,671 (Jul. 11, 1989) that an emitter switched thyristor (EST) shows a current saturation characteristic. M. S. Shekar et al. showed on IEEE Electron Device Lett. vol.12 (1991) p.387 that a dual channel emitter switched thyristor (EST) shows a current saturation characteristic up to a high-voltage area by actual measurement. Further, the inventor et al. disclosed the analysis results of FBSOA (forward bias safe operation area) and RBSOA (reverse bias safe operation area) of the EST on Proc. IEEE ISPSD '93, p.71 and Proc. IEEE ISPSD '94, p.195, and first opened the way for device development having a safe operation area at the load short-circuiting time in the voltage-driven thyristors. FIG. 11 shows the device structure of the EST.
As seen in the figure, the device comprises a first p base region 4, a p.sup.+ well region 5 of a deep diffusion depth occupying a part of the first p base region 4, and a second p base region 6 formed on the surface layer of an n base layer 3 located via an n buffer layer 2 on a p emitter layer 1, an n source region 7 formed on the surface layer of the first p base region 4, and an n emitter region 8 formed on the surface layer of the second p base region 6. A gate electrode 10 is disposed via a gate oxide film 9 extending from the portion of the first p base region 4 sandwiched between the n source region 7 and the exposure part of the n base layer 3 to the portion of the second p base region 6 sandwiched between the n emitter region 8 and the exposure part of the n base layer 3. However, the length of every region in the Z direction is limited and the first p base region 4 and the second p base region 6 are connected on the outside and the p.sup.+ well region 5 is formed like an L letter on the outside. A cathode electrode 11 coming in contact with the surface of the p.sup.+ well region 5 is also in contact with the surface of the n source region 7. On the other hand, an anode electrode 12 is disposed on the full rear face of the p emitter layer 1.
If a positive voltage is applied to the gate electrode 10 with the cathode electrode 11 grounded and a positive voltage applied to the anode electrode 12, an inversion layer (partial accumulation layer) is formed below the gate oxide film 9 and lateral MOSFET is turned on, whereby first electrons pass from the cathode electrode 11 via the n source region 7 through the inversion layer (channel) of the surface layer of the first p base region 4 and are supplied to the n base layer 3. The electrodes serve as base current of a pnp transistor consisting of the p emitter layer 1, the n buffer layer 2 and n base layer 3, and the first and second p base regions 4 and 6 and the p.sup.+ well region 5, whereby the pnp transistor operates. Then, holes are injected from the p emitter layer 1 and flow through the n buffer layer 2 and n base layer 3 into the first p base region 4; some of the holes flow into the second p base region 6. The holes flow in the Z direction below the n emitter region 8 into the cathode electrode 11 (IGBT mode). When the current furthermore increases, the pn junction between the n emitter region 8 and the second p base region 6 is forward-biased and a thyristor section consisting of the p emitter layer 1, the n buffer layer 2 and n base layer 3, the second p base region 6, and the n emitter region 8 is latched up. (This operation is called thyristor mode.) To turn off the EST, the potential of the gate electrode 10 is lowered to the threshold value of the lateral MOSFET or less and the MOSFET is turned off, whereby the n emitter 8 is potentially isolated from the cathode electrode 11 and the thyristor operation is stopped.
FIGS. 12 and 13 are sectional views of improved ESTs described in U.S. Pat. Nos. 5,317,171 (May 31, 1994) and 5,319,222 (Jun. 7, 1994) according to the invention of M. S. Shekar et. al. Particularly, the improved EST in FIG. 13 is intended for lower on-state voltage unlike the EST shown in FIG. 11.
FIG. 14 is a sectional view of an FET control thyristor described in U.S. Pat. No. 4,502,070 (Feb. 26, 1985) according to the invention of Leipold et. al, characterized in that no electrode is in contact with the top of a second p base region 6.
As seen from the description made so far, the EST shown in FIG. 11 uses holes flowing through the second p base region 6 in the Z direction to forward-bias the pn junction between the second p base region 6 and the n emitter region 8, thus the degree of the forward bias lessens as approaching the contact portion between the cathode electrode 11 and the second p base region 6. This means that the injection amount of electrodes from the n emitter region 8 is not uniform along the Z direction in the pn junction. If the EST is turned on from such an on state, the junction near the contact portion with the cathode electrode 11 shallowly forward-biased is first recovered and the portions distant from the contact portion with the cathode electrode 11 is not readily recovered. Thus, current concentration at the off time is easily incurred and the destruction resistance amount at the turn-off time lessens.
The device in FIG. 12 does not differ from the EST in FIG. 11 in operation principle; a cathode electrode 11 extends in the Y direction and comes in direct contact with the surface of a second p base region 6, thus the turn-off speed can be made fast, and since hole current in the Z direction is not used, uniform on operation is enabled. However, if a pn junction between an n emitter region 8 and the second p base region 6 is turned on at the thyristor operation time, then uneven injection of minority carriers occurs in the horizontal direction (Y direction) and lowering the on-state voltage as expected does not occur. To solve this problem, for example, if the impurity concentration of the second p base region 6 is lowered and resistance thereof is raised, a depletion layer is punched through in the n emitter region 8 at the forward withstand voltage time and sufficient withstand voltage is not produced.
The device shown in FIG. 13 has a structure wherein an n emitter 8 extends off a second p base region 6 to furthermore lower on-state voltage; it has a disadvantage in that the structure does not produce forward withstand voltage.
With the device shown in FIG. 14, an n emitter region 8 and a second p base region 6 are completely separated from a cathode electrode 11, thereby preventing uneven thyristor operation from occurring. However, since some of electrons supplied from an n source region 7 in the thyristor mode are not directed toward an n emitter region 8 and flow into an n base layer 3, the device has a disadvantage in that the onstate voltage of the thyristor becomes high.